diff --git a/pcb/logic-controller.PrjPcb b/pcb/logic-controller.PrjPcb
index f540a9f..aef97c2 100644
--- a/pcb/logic-controller.PrjPcb
+++ b/pcb/logic-controller.PrjPcb
@@ -271,24 +271,24 @@ Variation9=Designator=D24|UniqueId=\GDITEQVM|Kind=1|AlternatePart=
 ParamVariationCount=0
 
 [Parameter1]
-Name=UT_Project_Name
-Value=Logic Controller
+Name=UT_BOM_Version
+Value=v1
 
 [Parameter2]
-Name=UT_PCB_Revision
-Value=r1
+Name=UT_Output_file_name
+Value=logic-controller
 
 [Parameter3]
 Name=UT_PCB_Designer
 Value=Andis Zīle
 
 [Parameter4]
-Name=UT_Output_file_name
-Value=logic-controller
+Name=UT_PCB_Revision
+Value=r1
 
 [Parameter5]
-Name=UT_BOM_Version
-Value=v1
+Name=UT_Project_Name
+Value=Logic Controller
 
 [Configuration1]
 Name=Sources
@@ -514,6 +514,12 @@ OutputDocumentPath14=
 OutputVariantName14=[No Variations]
 OutputDefault14=0
 PageOptions14=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
+OutputType15=PDF3D MBA
+OutputName15=PDF3D MBA
+OutputDocumentPath15=
+OutputVariantName15=
+OutputDefault15=0
+PageOptions15=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=A4|PaperIndex=9
 
 [OutputGroup4]
 Name=Assembly Outputs
@@ -871,6 +877,16 @@ OutputName10=Web Review Data
 OutputDocumentPath10=
 OutputVariantName10=
 OutputDefault10=0
+OutputType11=MBAExportPARASOLID
+OutputName11=Export PARASOLID
+OutputDocumentPath11=
+OutputVariantName11=
+OutputDefault11=0
+OutputType12=MBAExportSTEP
+OutputName12=Export STEP
+OutputDocumentPath12=
+OutputVariantName12=
+OutputDefault12=0
 
 [OutputGroup10]
 Name=PostProcess Outputs
diff --git a/pcb/source/index.SchDoc b/pcb/source/index.SchDoc
index 9e7cd9e..736aab2 100644
Binary files a/pcb/source/index.SchDoc and b/pcb/source/index.SchDoc differ
diff --git a/pcb/source/logic-controller.PcbDoc b/pcb/source/logic-controller.PcbDoc
index 5c49512..606b3ff 100644
Binary files a/pcb/source/logic-controller.PcbDoc and b/pcb/source/logic-controller.PcbDoc differ
diff --git a/pcb/source/outputs.SchDoc b/pcb/source/outputs.SchDoc
index db7b34a..31e385b 100644
Binary files a/pcb/source/outputs.SchDoc and b/pcb/source/outputs.SchDoc differ
diff --git a/pcb/source/power.SchDoc b/pcb/source/power.SchDoc
index 973028a..db17692 100644
Binary files a/pcb/source/power.SchDoc and b/pcb/source/power.SchDoc differ