Andis Zīle e655803c1f revision 1

2024-04-24 16:28:53 +03:00

..

block_diagram.SchDoc

revision 1

2024-04-24 16:28:53 +03:00

connector.SchDoc

Schematic design

2024-04-15 16:15:11 +03:00

cover_page.SchDoc

Schematic design

2024-04-15 16:15:11 +03:00

history.SchDoc

Ready for review

2024-04-24 09:19:23 +03:00

index.SchDoc

saved work

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inputs.SchDoc

Schematic design

2024-04-15 16:15:11 +03:00

logic-controller.PcbDoc

revision 1

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mcu.SchDoc

Ready for review

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miscellaneous.SchDoc

Schematic design

2024-04-15 16:15:11 +03:00

outputs.SchDoc

Done pcb design

2024-04-23 22:10:32 +03:00

power.SchDoc

Ready for review

2024-04-24 09:19:23 +03:00